Implementation of Efficient Parallel Prefix Adders for Residue Number System
نویسندگان
چکیده
منابع مشابه
Parallel Prefix Adder for High Dynamic Range Residue Number System
A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2 − 1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and...
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In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. A parallel prefix adder involves the execution of the operation in parallel which can be obtained by segmentation into smaller pieces. The binary addition is the basic arithmetic operation in digital circuits and it became essential in most of the digital systems including Arithmetic ...
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In many building blocks of microprocessors and digital signal processing chips, adders are frequently available in their critical paths. Adders can also be used for subtraction, multiplication and division. One of the important basic arithmetic operations is addition. There are several structures like Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA) to perform the addition. Parallel prefi...
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In this paper we explore the feasibility of implementing Residue Number System (RNS) based DSP algorithms on Lookup table based Field Programmable Gate Arrays (FPGAs). In this process, Binary Decision Diagrams are used for logic representation, and a new minimizing algorithm for incompletely specified functions is introduced. A sample residue arithmetic based design is presented along with prom...
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In this paper a systematic methodology for designing parallelprefix modulo 2 − 1 adders, for every n, is introduced. The resulting modulo 2 − 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims to the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal...
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ژورنال
عنوان ژورنال: International Journal of Computing and Digital Systems
سال: 2015
ISSN: 2210-142X
DOI: 10.12785/ijcds/040409